1. Field of the Invention
The present invention relates to a transistor structure, and more particularly to a vertical transistor and an array with vertical transistors.
2. Description of Related Art
In order to accelerate operating speed of dynamic random access memories (DRAMs) in integrated circuit products and to meet customers' demands on miniaturizing electronic devices, physical dimensions of transistors in a semiconductor apparatus are continuously reduced. Thereby, however, a short channel effect would occur in the transistors, and an On current is likely to decrease.
To resolve said issue, a conventional horizontal transistor is replaced by a vertical transistor, as proposed in U.S. Pat. No. 7,285,812. Specifically, the vertical transistor is formed both in a trench and above the trench. On the other hand, another conventional solution aims at forming a gate at an edge of an epitaxial post, as proposed in U.S. Pat. No. 7,042,047. Nonetheless, said structures can be further improved in terms of controlling channels thereof.